In design and manufacture of an LSI (Large Scale Integration), various tests are performed before the products are put into the market. For example, a mass-production test and a POST (Power On Self Test) are known as tests which are performed by mounting an LSI on a device such as a computer. In such tests, a diagnosis as to whether or not an LSI is normally operating is made by executing a test program in a testing device on which the LSI is mounted.
However, many LSIs have FIFO (First-In First-Out) type storage devices. In the FIFO type storage devices, data which are earlier inputted are earlier outputted. Hereinafter, buffer circuits in which input/output control is performed in a first-in first-out manner are referred to as FIFOs. The FIFOs are constituted by flip flop circuits or a RAM (random access memory), and used in various portions of LSIs, for example, as a packet transmission queue, a packet reception queue, or as a memory for temporarily storing control information. In the case where an error correction code (ECC) generated by hardware is attached to data at each address in a FIFO, the data is protected on an address-by-address basis.
The testing of an LSI having a FIFO includes an operational test of the FIFO. For example, a fault diagnosis of the FIFO is performed by inputting predetermined data into the LSI in accordance with a test program for a mass-production test or a POST. The fault detection in the FIFO memory is performed on the basis of both of disparity between an expected value and a value obtained by execution of the test program and detection of an ECC error.
The faults detected by execution of the tests of the FIFOs include permanent faults and delay faults. The permanent fault means a state in which the value of a bit in a FIFO is stuck at “0” or “1” because of short circuit in the wiring or the like. For example, in the case where a permanent fault in which a bit value is stuck at “0” occurs at a bit in a FIFO, the value of the bit remains “0” even when the value “1” is written in the bit. Therefore, in order to detect both of the permanent fault in which the value of a bit is stuck at “0” and the permanent fault in which the value of the bit is stuck at “1”, the test program is required to generate a test pattern which writes each of the values “0” and “1” in the bit. The delay fault means a failure in readout from a FIFO which is caused by an excessive delay beyond the operational cycle. For example, in order to detect a delay fault in an address, the test program needs to contain a test pattern in which the value of data in the address is different from the value of data in the preceding address, e.g., the value of the test data in the address needs to be “1” and the value of the test data in the preceding address needs to be “0”. (See, for example, Japanese Laid-open Patent Publications Nos. 01-309154, 05-165734, and 2006-208077.)
However, in some case, it is difficult to write an arbitrary test pattern in a FIFO. For example, in the case where both of a header and data of a packet are written in a FIFO, arbitrary values can be written in the data area by a test program. However, the fields constituting the header area respectively have meanings such as address and type. Therefore, a test program needs to be produced on the basis of the recognition as to how the respective fields are written in the FIFO. In addition, in the case where the data written in the FIFO contains the ECC, the test program needs to be produced on the basis of the recognition of the generator polynomial of the ECC. That is, in order to improve the fault detection rate, the test program needs to be produced on the basis of full knowledge of complex hardware logic circuitry so that the test program generates a desired test pattern.
Alternatively, it is possible to improve the fault detection rate as much as possible by producing a test pattern generating a long random pattern without knowledge of complex hardware logic circuitry. However, execution of the test program generating a long test pattern on respective LSIs during mass-production lowers the manufacturing efficiency, so that the use of the long random pattern is not realistic. Thus, it is impossible to achieve a high fault detection rate in the case where production of a test pattern for a FIFO based on full knowledge of complex hardware logic circuitry is difficult or in the case where diagnosis of a FIFO by use of a long random pattern is difficult.
As explained above, in some cases, although the fault detection rate in detection of the permanent fault and the delay fault in a FIFO depends on a test pattern generated by a test program, data to be written in the FIFO may not be directly produced by the test program, so that it is difficult to achieve a high fault detection rate.
Incidentally, LIFO (Last-in First-out), as well as FIFO, is also known as a manner of writing and reading data in a predetermined order. According to LIFO, data which are later inputted are earlier outputted. Hereinafter, buffer circuits in which input/output control is performed in a last-in first-out manner are referred to as LIFOs. In LIFOs, as in FIFOs, a high fault detection rate may not be achieved because it is difficult to write an arbitrary test pattern in LIFOs.